Fluxus-Q

Served

TransmonCross Hamiltonian

The circuit Hamiltonian of a TransmonCross qubit coupled to a readout resonator — qubit frequency f01, anharmonicity, resonator frequency, coupling g and dispersive shift χ — from layout geometry and junction inductance.

For: Transmon designers working in the qiskit-metal / SQuADDS TransmonCross geometry family who want Hamiltonian parameters without a capacitance solve per iteration.

0.30%

charging-energy error vs HFSS

median · 1.67% p95 · grouped split · n = 1,934

Status. Served on the hosted Fluxus API, with inverse design.

Engine. Data-trained surrogate for the capacitance step; every later step (charging energy, f01, anharmonicity, g, χ) is exact physics, not learned.

Reference. SQuADDS HFSS Maxwell capacitance matrices for the TransmonCross family — electromagnetic simulation, not measured silicon.

API

Endpoints

POST/v1/fluxus/qem/cross

geometry → Hamiltonian, optional calibrated intervals

POST/v1/fluxus/inv/cross

target Hamiltonian → ranked geometries

Base URL https://api.cogitan.ai, bearer key from an approved account. Read GET /v1/fluxus/capabilities first: it states the same fidelity, validation, envelope and refusal conditions as this page. Access model.

Inputs

What you send

cross_length_um

µm — swept axis

claw_length_um

µm — swept axis

ground_spacing_um

µm — swept axis

junction_lj_nh

nH — free; sets the Josephson energy, not the capacitance

length_um, kind, coupling_length_um

the readout resonator, same envelope as the resonator surrogate

intervals

optional; adds calibrated intervals on every output

Outputs

What comes back

f01

GHz — qubit transition frequency

anharmonicity

MHz

fr

GHz — readout resonator frequency

g

MHz — qubit–resonator coupling

χ

MHz — dispersive shift

Validation

Measured against what, and how

Reference. SQuADDS HFSS Maxwell capacitance matrices for the TransmonCross family — electromagnetic simulation, not measured silicon.

Sample. 1,934 simulated devices.

Split. Grouped 5-fold cross-validation holding out whole cross lengths, so every test device has a cross length the model never saw at any claw length.

Shanto et al., SQuADDS: a validated design database and simulation workflow for superconducting qubit design, Quantum 8, 1465 (2024)

Cross-to-cross capacitance

0.30% median

1.66% p95

Cross-to-claw capacitance

0.56% median

1.75% p95

Charging energy EC

0.30% median

1.67% p95

Interval coverage

98.4%

against a 95% target

Envelope

Where the answer is trusted

cross_length_um

90 – 420 µm

claw_length_um

70 – 400 µm, and ≤ cross length − 20 µm

ground_spacing_um

4.1 – 10 µm

cross gap / cross width

30 µm / 30 µm (fixed)

claw width / claw gap

15 µm / 5.1 µm (fixed)

junction_lj_nh

free

Refusals

When you get no number

Outside the envelope — including any change to a fixed dimension — returns HTTP 422 with code outside_envelope and {field, value, allowed}, so an agent can repair the call without parsing prose.

Known limits

What it does not do

Only 3 of the 7 geometry dimensions vary in the reference data. The other four are fixed, so this covers one slice of the TransmonCross family, not the family.
The cross-length × claw-length grid is only 51.5% populated, because the claw can never exceed the cross length minus 20 µm.
The split is grouped because a random split flatters this grid: random K-fold reports 0.12% median on cross-to-cross capacitance, which measures interpolation between adjacent grid points, not a new geometry. We quote the grouped 0.30%.
The resonator half of the chain inherits the resonator surrogate's envelope and error.

Inverse design

POST /v1/fluxus/inv/cross takes any subset of f01, anharmonicity, fr, g and χ as targets and returns ranked TransmonCross geometries inside the envelope.
There is no separate accuracy metric for inverse design: every returned candidate is re-solved by the forward chain above, so its numbers carry the forward chain's error. A returned design is a proposal to simulate, not a fabrication instruction.

Every figure on this page compares against a simulator or a published device measurement. None of it is a prediction of your fabricated hardware. For one certification-grade answer, run the full reference; this is for screening many designs cheaply and spending solver time on the survivors.