Fluxus-S · SFQ logic
Deployed todayVerify SFQ logic
without the JoSIM queue.
Fluxus-S is the superconducting-digital half of Fluxus: margin, timing, yield, and design-rule verification for RSFQ single-flux-quantum cells — layout-native, JoSIM-accurate, with a calibrated confidence bound on every prediction. It is our deployed, process-validated product. Point it at a cell library and a PDK and screen a chip's worth of cells before lunch.
Delivery · API and CLI
A design loop, not an overnight queue.
Point the API or CLI at a cell library and a PDK and you get propagation delay, switching margin, and design-rule compliance for every cell with a confidence bound — the low-confidence handful auto-flagged for a full SPICE check. Trained per process node on your reference simulator.
API + CLI · licensed per team
RSFQ circuit verification · MIT-LL SFQ5ee+
import cogitan
# verify a whole cell library in one batch
results = cogitan.verify(
path = "./layouts/sfq5ee+",
pdk = "mit-ll-sfq5ee+",
batch = True,
)
for cell, r in results.items():
print(
f"{cell:<14} {r.delay:>5.1f}
f" ± {r.sigma:.1f} ps {r.status}"
)$ cogitan verify ./layouts/sfq5ee+
SPLIT_v1_a 17.2 ± 1.4 ps ✓
SPLIT_v2_b 18.9 ± 1.1 ps ✓
DFF_x3_c 22.1 ± 5.8 ps → spice
AND2_v1_d 14.4 ± 1.6 ps ✓
...
─────────────────────────────────
1,000 cells 4.8s (JoSIM: ~85 min)
997 pass · 3 → spice fallback
~10³×
faster than JoSIM margin runs
2.1 ps
chain delay RMSE, held-out chains vs JoSIM
100%
DRV detection from layout, held-out cells
grouped split
no held-out cell seen at any training stage
Capabilities · the whole SFQ surface
Every feature, with the number behind it.
Margin verification from netlists, plus a layout-native deep screener that reads GDS geometry directly — each line carrying the metric that backs it.
Margins & verification
metric
Analytic margins
functional verdict + bias / Ic bands
Assembled-chain margin
shared-rail window, whole circuit
Three-engine validation
one operating point
ERSFQ / eSFQ bias
resistor vs zero-static sizing
Process portability
one netlist, retargeted
One-click datasheet
characterize a cell in one call
Deep screening · layout-native
metric
GDS-native inference
reads layout geometry directly — no netlist
Chain delay
222 held-out 2–7-cell chains vs JoSIM
DRV detection
from layout geometry, held-out cells
Calibrated uncertainty
twin-model disagreement, per cell
Chip-scale throughput
warm batch
Deep-engine figures are measured vs JoSIM on the ColdFlux SFQ5ee+ family under a grouped cell-level split — no clean or mutated variant of a held-out cell appears at any training stage. Single-cell delay carries its stated RMSE, so for fast cells it reads near the noise floor and is flagged; the screening grade, design-rule flags, and chip-scale batch are where the deep engine earns its keep.
Process nodes
Validated where it counts.
Fluxus-S is validated on MIT-LL SFQ5ee+ and retargets to other fab nodes from one netlist. Per-process calibration is a fixed-scope engagement: we train on your reference simulator and hand you the validated endpoint with its validity report.
Building SFQ control for qubits?
Fluxus-S and Fluxus-Q together enable co-design — simulating SFQ control logic against qubit Hamiltonians for flux crosstalk, timing, and heat load at 10 mK. Own both, or start with the half you need now.
Designing RSFQ logic?
Let's talk.
If your design loop is bottlenecked on JoSIM margin runs, we'd like to understand it — and train Fluxus-S on your process.
Get in touch