Cogitan

Fluxus-Q · qubit / cQED

In build · Phase 0

The Hamiltonian,
before the solve finishes.

Fluxus-Q is the qubit half of Fluxus: layout → eigenmodes, Hamiltonian, inverse design, and frequency-collision yield for superconducting cQED chips. Today the answer costs ~1 hour of HFSS per resonator and ~4.7 hours per design iteration. Fluxus-Q makes it a sub-second function with calibrated error bars — and full-fidelity verification one keystroke away.

The bottleneck

One question, asked constantly.

Every superconducting qubit team asks the same thing on every iteration: what Hamiltonian does this layout give me, and will it yield? At full fidelity that answer is an electromagnetic eigenmode solve — and design is never one solve. It is a sweep.

Wall-clock, at full fidelity

One eigenmode solve, single resonator (HFSS/Palace)~1 hr
One qubit–resonator design iteration~4.7 hrs
Screening 10,000 candidate geometries with the solver~1.1 CPU-years
Chip-scale solvesexhaust 768 GB workstations

The functions · the qubit design loop

Four functions, one spine.

Each is a typed call with calibrated confidence and a verify path. Out-of-envelope inputs abstain and route to a full-fidelity run — never a silent extrapolation.

QEM

Eigenmodes

Layout → resonant modes: frequency, quality factor, and participation ratios per mode. The ~1-hour HFSS/Palace eigenmode solve becomes a sub-second call, with a calibrated interval and a source label on every number.

HAM

Hamiltonian

Layout or netlist → the full dispersive Hamiltonian: qubit and resonator frequencies, anharmonicity, couplings g, dispersive shift χ, and Purcell estimates — the eigenmode + EPR post-processing chain in one function.

INV

Inverse design

Hand Fluxus-Q a target Hamiltonian — f01 = 4.8 GHz, fr = 7.0 GHz — and it returns ranked candidate geometries. The surrogate proposes across a screened space; the oracle disposes, re-solving every finalist so candidates are verified, not just predicted.

YLD

Frequency-collision yield

Chip netlist + process scatter → a Monte Carlo over 10⁴–10⁶ virtual chips, implementing all seven Hertzberg et al. (2021) collision rules, with a yield-versus-frequency-spread curve. The product only a fast Hamiltonian predictor makes possible.

Where it stands · honest by default

A v0 pipeline, becoming a product.

Today's Fluxus-Q surrogates are trained against a fast analytic cQED oracle — Koch et al. (2007) for the transmon, Göppl et al. (2008) for the CPW resonator, standard dispersive coupling. Every accuracy figure below is surrogate-versus-oracle, not surrogate-versus-measurement.

Phase 0 makes it real: retraining on AWS Palace electromagnetic solves across canonical cell families, then a public held-out benchmark against SQuADDS experimental devices. We publish the validation before we claim the number — that is the whole brand.

Surrogate vs. analytic oracle · 10k held-out

p95 rel. error

f01Qubit frequency
0.38%
anharmonicityTransmon α
0.54%
frResonator frequency
0.50%
gQubit–resonator coupling
1.31%
χDispersive shift
0.02 MHz median abs.*

≥89%

conformal coverage at α = 0.1

7 / 7

Hertzberg (2021) collision rules

Palace

EM ground truth — Phase 0

* χ has a heavy relative-error tail near the dispersive poles inside the sampled envelope; median absolute error is the representative figure. Nothing here is fab-measured yet — process-registry entries are literature-derived anchors with stated sources, not validated PDK data. We say so on every surface.

On the roadmap

Design, then discovery.

The core loop ships first. Readout/code co-design follows — a function that engineers a logical readout so its back-action is an error the code already corrects, grounded in our own theory.

QEM · HAM — eigenmodes & HamiltonianCore build
INV — inverse designBuilt
YLD — frequency-collision yieldBuilt
RDO — readout / code co-designPlanned

Controlling qubits with SFQ?

Fluxus-Q and Fluxus-S together enable co-design — SFQ control logic simulated against qubit Hamiltonians for flux crosstalk, timing, and heat load at 10 mK. Cogitan is the only vendor with a deployed SFQ surrogate to pair with the qubit half.

The Fluxus suite

Designing qubit chips?
Shape Fluxus-Q with us.

We are opening a small number of design-partner slots for Phase 0 — early access to the qubit functions, calibrated to your process, in exchange for shaping what ships. If you run the EM-to-Hamiltonian loop constantly, let's talk.

Get in touch